To the third bullet: one example is x86's LOCK instruction prefix. When used with an instruction, the CPU makes sure that, while executing that instruction, either the bus is locked, or the area of memory being modified is completely contained in that core's cache line. More detailed description in Section 8.1.4 of this part of the x86 manual.
ayy_lmao
Do high-level languages compile atomic code blocks to optimized mutex's? Or are they sophisticated enough to compile these to hardware supported operations
rrudolph
How do atomic locks work with block shared memory / caching schemes that we learned in the most recent lecture?
Levy
@ayy_lmao Actually I don't think most generic programming language compilers now have the capabilities of compiling atomic blocks to hardware operations. And the fact is, by looking at atomic operation package in one language (e.g. "sync/atomic" in Golang), you will realize that built in atomic operation support is extremely poor
To the third bullet: one example is x86's LOCK instruction prefix. When used with an instruction, the CPU makes sure that, while executing that instruction, either the bus is locked, or the area of memory being modified is completely contained in that core's cache line. More detailed description in Section 8.1.4 of this part of the x86 manual.
Do high-level languages compile atomic code blocks to optimized mutex's? Or are they sophisticated enough to compile these to hardware supported operations
How do atomic locks work with block shared memory / caching schemes that we learned in the most recent lecture?
@ayy_lmao Actually I don't think most generic programming language compilers now have the capabilities of compiling atomic blocks to hardware operations. And the fact is, by looking at atomic operation package in one language (e.g. "sync/atomic" in Golang), you will realize that built in atomic operation support is extremely poor