Basic Concepts of Program Instances and Gangs of Program Instances can be found here
apr
Someone made a good point in class about the cache misses. When multiple gang members are trying to access memory that would be stored contiguously as one line in the cache, then does the hardware choose which of those SIMD gang members will cause the cache miss and eventual population of the cache? Which part of the processor deals with this level of synchronization?
shpeefps
I'm not sure it's important which gang member causes the cache miss unless there is a chance that the gang member's program would also result in a partial hit to an extent. I would like to know at what stage the gangs and the assignment of resources to gangs are decided. Is it done at compile time or dynamically?
albusshin
Multiple processors accessing the same cache line would result in false sharing, meaning there is contention for the cache line.
Basic Concepts of Program Instances and Gangs of Program Instances can be found here
Someone made a good point in class about the cache misses. When multiple gang members are trying to access memory that would be stored contiguously as one line in the cache, then does the hardware choose which of those SIMD gang members will cause the cache miss and eventual population of the cache? Which part of the processor deals with this level of synchronization?
I'm not sure it's important which gang member causes the cache miss unless there is a chance that the gang member's program would also result in a partial hit to an extent. I would like to know at what stage the gangs and the assignment of resources to gangs are decided. Is it done at compile time or dynamically?
Multiple processors accessing the same cache line would result in false sharing, meaning there is contention for the cache line.