Is there a chance that the data in different memory would exchange to improve the efficiency of programs?
slowloris
Adding on to harlenVII's question, is it possible that the same data is in multiple memories? Perhaps data X started in memory of processor A, but a core in processor B needed it so copied that data into processor B's memory for easier access. Though, I am not sure how the data would be kept up to date if either of the processors were to update it. Perhaps I just am not understanding how this all works entirely.
firebb
I think here we use several DRAMs to form a larger memory space, in which each DRAM has part of the physical address space, so I think there should be no sharing between DRAMs. It's not like caches in the processors which is the copy of the content of the memory.
paracon
@slowloris,@harelenVII, I believe the presence of cache helps in amortising the cost over time. Though the memory access in non-uniform, the interconnects should still be quite fast since its on-core (like the PCI-Interconnect between two cores.) So after an initial access, the data will become cache-local to the core. Another issue that might come in here is that we would have to use write-back policy for consistency, as write-through can cause too many stalls.
Is there a chance that the data in different memory would exchange to improve the efficiency of programs?
Adding on to harlenVII's question, is it possible that the same data is in multiple memories? Perhaps data X started in memory of processor A, but a core in processor B needed it so copied that data into processor B's memory for easier access. Though, I am not sure how the data would be kept up to date if either of the processors were to update it. Perhaps I just am not understanding how this all works entirely.
I think here we use several DRAMs to form a larger memory space, in which each DRAM has part of the physical address space, so I think there should be no sharing between DRAMs. It's not like caches in the processors which is the copy of the content of the memory.
@slowloris,@harelenVII, I believe the presence of cache helps in amortising the cost over time. Though the memory access in non-uniform, the interconnects should still be quite fast since its on-core (like the PCI-Interconnect between two cores.) So after an initial access, the data will become cache-local to the core. Another issue that might come in here is that we would have to use write-back policy for consistency, as write-through can cause too many stalls.