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yeq

We should be careful about write-back buffer otherwise, the memory consistency might be violated. Consider the following scenario. Processor A holds X in the Modified state. Then Processor B requests to read the value of X, so it sends a BusRd. Noticing this request, A is supposed to flush the value of X to memory so that B could get the up-to-date value. However, with write-back buffer exists, the flushing of X will be deferred to a later time, resulting B retrieves an old version of X.

vadtani

A way to prevent the scenario which @yeq mentioned is that when A snoops this request it can respond with the data from the write-back buffer instead of just looking into the cache.

BestBunny

@yeq I believe it was mentioned in lecture that with a write back buffer, caches would look in the write-back buffer whenever requesting data to make sure what is received is the most up-to-date value.

I still have a question regarding the write back buffer implementation though. What happens if the write-back buffer is full, cache A wants to evict a dirty line and replace it with line L in exclusive access state, cache B wants exclusive access to line L, and anything but the write-back buffer has access to the bus? Not too sure if that's a good scenario, but if the write back buffer gets full, don't we still have the same situation as if we didn't have a write back buffer but now just with the additional cost of caches having to also examine the write-back buffer?

chenboy

@BestBunny I agree that if write-back buffer is full then we get the same situation as if we didn't have a write back buffer. But I think write back is not happening that frequently so this buffer will be useful most of the time.

pk267

@BestBunny: The flush would have to happen at some point in time or another. WHat write-back buffer is doing is kinda like expanding the size of the cache while decreasing the time to service a processor's requests. Also, since all flushes are deferred, they can be clubbed together and happen in the background when the processor is free.

Correct me if you think it is wrong!

firebb

I think it is even possible to flush the writeback buffer without processor involving. Since the writeback cache aims to hide the latency of evicting some of the cache lines. These cache lines may not be requested by other processors immediately, so eventually flushing them back to memory at some point would be fine. The processor could just trigger a signal to flush back the writeback buffer and do not need to block until it is done.