The atomic bus acted as a bottleneck. So we want to be able to perform operations in between the request and response. This allows room for race conditions however. Since the atomic bus bottlenecked the timeline, it forced a serial ordering on the operations.
chenh1
What if p2 sends BusUpg of A? Because the memory is still fetching, there will be no cache line A in P1.
The atomic bus acted as a bottleneck. So we want to be able to perform operations in between the request and response. This allows room for race conditions however. Since the atomic bus bottlenecked the timeline, it forced a serial ordering on the operations.
What if p2 sends BusUpg of A? Because the memory is still fetching, there will be no cache line A in P1.