I don't understand why the response for memory transaction 1 would ever not be sent immediately after the first ACK. Is it just because no responses are ready to be sent?
firebb
@rc0303 I think you are probably right. It is possible that the processor needs to respond to transaction 1 is busy doing other things, so it just delay its response.
chenh1
I think that maybe the latency of the first transaction is very long and make the response late.
Drizzle
Is this pipelining performed in hardware, or in software? I was under the impression that it was performed on the chip by default.
I don't understand why the response for memory transaction 1 would ever not be sent immediately after the first ACK. Is it just because no responses are ready to be sent?
@rc0303 I think you are probably right. It is possible that the processor needs to respond to transaction 1 is busy doing other things, so it just delay its response.
I think that maybe the latency of the first transaction is very long and make the response late.
Is this pipelining performed in hardware, or in software? I was under the impression that it was performed on the chip by default.
@Drizzle Isn't all of this done on chip?