Q1: The thread on P0 holds the lock from the point where the t&s command sets the lock variable to 1, until the point where the the lock variable is set back to 0 (releasing the lock). The duration of time is represented by the yellow region on the previous slide.
Q2: P0's cache contains a valid copy of the cache line when it does the original write to take the lock and then at the end, when it does another write to release the lock.
BestBunny
To add on to Q2, during the period when P0 doesn't contain a valid copy of the cache line (the yellow region) the ownership of the cache line constantly switches between P1 and P2. As a result, these processors generate large amounts of interconnect traffic that may even delay the execution of P0 (which owns the memory address/lock). This behavior also causes P0 to have a cache miss when trying to unlock at the end of the critical region.
shpeefps
I'm a little confused about Q2. When you say P0 will have a valid cache line when it releases the lock, do you mean right after it releases the lock? If you meant right before, could you explain how?
POTUS
@shpeefps P0 has a valid cache line from the time it does the (second) BusRdX request until the point when P2 issues a BusRdX.
Q1: The thread on P0 holds the lock from the point where the t&s command sets the lock variable to 1, until the point where the the lock variable is set back to 0 (releasing the lock). The duration of time is represented by the yellow region on the previous slide.
Q2: P0's cache contains a valid copy of the cache line when it does the original write to take the lock and then at the end, when it does another write to release the lock.
To add on to Q2, during the period when P0 doesn't contain a valid copy of the cache line (the yellow region) the ownership of the cache line constantly switches between P1 and P2. As a result, these processors generate large amounts of interconnect traffic that may even delay the execution of P0 (which owns the memory address/lock). This behavior also causes P0 to have a cache miss when trying to unlock at the end of the critical region.
I'm a little confused about Q2. When you say P0 will have a valid cache line when it releases the lock, do you mean right after it releases the lock? If you meant right before, could you explain how?
@shpeefps P0 has a valid cache line from the time it does the (second) BusRdX request until the point when P2 issues a BusRdX.