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acortes

How is the Test and set instruction implemented?

bpr

@acortes, it is a single instruction. We know some details about how "atomic" is implemented, as discussed in next lecture. The Intel architecture manual talks about test-and-set as:

MOV EAX, 1
XCHG EAX, lockvar ;Try to get lock
CMP EAX, 0 ;Test if successful

So on x86, there is no actual "ts" instruction, but a 3-op sequence.

MangoSister

Should the store (unlock) here also be atomic?

bpr

@MangoSister, no. Atomic is required for the instructions that are doing a read-modify-write. Test-and-set returns the old value (i.e. read), and also must write to the location. The store in the unlock code is just writing and is therefore "atomic".