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tclarke

I'm confused as to why the individual processors have to invalidate their cache lines. It seems like they shouldn't since when processor 2 reads the lock value after the BusRdX, it doesn't write to the memory location because it doesn't acquire the lock. Can someone help me out on this?

EggyLv999

I believe it acquires with the intent to write, so when it fails to acquire, it invalidates the line since it only cares about getting the line in an exclusive state. This is probably because test and set is atomic, so it can make such a request knowing that it must write.

Tengjiao

So is it a hardware level decision of this invalidation? Whether the test and set succeed or fail, the cache line will be invalidated. Couldn't it be smarter as @tclarke says?

lusiliang93

I think BusRdx means Processor 1 obtains copy of line with intent to modify. That's why it should be an exclusive state and other processors must invalidate that line(not only just because of atomic state). Like @EggyLv999 said, the line has to be invalidated by other processors so as to maintain an exclusive state.