BusRd notifies all processors the issuing processor is pulling the line into its cache for read-only access, and also fetches the line from memory.
BusRdX notifies all processors the issuing processor is pulling the line into its cache for read-write access, and also fetches the line from memory.
BusWB writes a cache line back to memory.
This comment was marked helpful 0 times.
mitraraman
Since BusRd is a transaction for read-only access, why must the processor fetch the line from memory? This transaction does not change other processors' behaviors with that cache line, correct?
This comment was marked helpful 0 times.
martin
I believe this transaction doesn't change other processors' behaviors. Processor uses BusRd to get fresh data from memory when other processor has exclusive ownership of the data.
This comment was marked helpful 0 times.
kayvonf
@mitraraman, @martin: The answer to your question is provided in the precise description of the MSI coherence protocol on the next slide. There is no concept of "stale data" sitting in the cache. Either the line is valid (indicated by a line in the M or E state) and it contains the most recent copy of the data, or it is invalid (and thus can be thought of as containing no data at all).
Processors must broadcast a BusRd operation on the interconnect to inform all other processors of their intent to read. The coherence protocol requires the cache with the line in the exclusive state (if such a cache exists) to move the line to the S state (and thus perform no further writes) before the read by another processor is permitted to occur. Otherwise, the write serialization requirement of memory coherence could be violated.
This comment was marked helpful 0 times.
chaominy
How does a processor determine whether the current request is a BusRd or a BusRdX? Does this only depend on the current single instruction, or is it influenced by the following instructions?
This comment was marked helpful 0 times.
kayvonf
@chaominy: When a read or write instruction issued by the processor triggers a cache miss, the cache must broadcast a BusRd or a BusRdX message (respectively) for the line to all other processors. See the protocol description on the next slide.
Specifically:
BusRdnotifies all processors the issuing processor is pulling the line into its cache for read-only access, and also fetches the line from memory.BusRdXnotifies all processors the issuing processor is pulling the line into its cache for read-write access, and also fetches the line from memory.BusWBwrites a cache line back to memory.This comment was marked helpful 0 times.
Since
BusRdis a transaction for read-only access, why must the processor fetch the line from memory? This transaction does not change other processors' behaviors with that cache line, correct?This comment was marked helpful 0 times.
I believe this transaction doesn't change other processors' behaviors. Processor uses
BusRdto get fresh data from memory when other processor has exclusive ownership of the data.This comment was marked helpful 0 times.
@mitraraman, @martin: The answer to your question is provided in the precise description of the MSI coherence protocol on the next slide. There is no concept of "stale data" sitting in the cache. Either the line is valid (indicated by a line in the M or E state) and it contains the most recent copy of the data, or it is invalid (and thus can be thought of as containing no data at all).
Processors must broadcast a
BusRdoperation on the interconnect to inform all other processors of their intent to read. The coherence protocol requires the cache with the line in the exclusive state (if such a cache exists) to move the line to the S state (and thus perform no further writes) before the read by another processor is permitted to occur. Otherwise, the write serialization requirement of memory coherence could be violated.This comment was marked helpful 0 times.
How does a processor determine whether the current request is a BusRd or a BusRdX? Does this only depend on the current single instruction, or is it influenced by the following instructions?
This comment was marked helpful 0 times.
@chaominy: When a read or write instruction issued by the processor triggers a cache miss, the cache must broadcast a
BusRdor aBusRdXmessage (respectively) for the line to all other processors. See the protocol description on the next slide.This comment was marked helpful 0 times.