Parallel Computer Architecture and Programming (CMU 15-418/618)

This page contains practice exercises to help you understand material in the course. Reference material and lecture videos are available on the References page.

Self-Check Exercises

Exercise 1: A Task Queue on a Multi-Core, Multi-Threaded CPU
Concepts tested: multi-core architecture, hardware multi-threading

Exercise 2: Be a Processor Architect + Data-Parallel Histogram Implementation
Concepts tested: multi-core architecture, data-parallel thinking, CUDA language semantics

Exercise 3: More on Histograms + Angry Students
Concepts tested: invalidation-based cache coherence, workload balance

Exercise 4: Cloning Prof. Kayvon + A Coherence Question
Concepts tested: request scheduling, cache coherence, atomic operations

Exercise 5: Two Concurrent Linked Lists
Concepts tested: fine-grained locking, transactional memory

Exercise 6: Controlling DRAM + Building a Mesh Network
Concepts tested: how DRAM works, basics of routing in an interconnection network

Programming Assignments

Assignment 1: Analyzing Parallel Program Performance on a Quad-Core CPU

Assignment 2: A Simple Renderer in CUDA

Assignment 3: Two Algorithms, Two Programming Models

Assignment 4: A Simple, Elastic Web Server