What does it mean by that one instruction is executed per clock? Does it mean clock cycle? Because if it means per clock cycle, I'm assuming it's only for this simple example processor, because I learned in 18-240 that each instruction took like 5-6 clock cycles.
kayvonf
@abist. Good question. Yes, I do mean one instruction per clock cycle. In 18-240 you learned that the latency of instructions a small number of clocks, which is true. Modern processors achieve a throughput of one instruction per clock by overlapping execution of several instructions using pipelining (which I won't describe here, but perhaps you discussed it in 240). So for now in the course, it's perfectly reasonable to think of this fictitious processor completing one instruction per clock.
landuo
I think there are normally 5 stages of instruction processing within the processor (fetch, decode, execute, memory access and write back), and the processor will fetch one more instruction when the previous one has moved to decoding phase. And when the first fetched instruction go through to execute stage, the second one move on to decode and the third one is fetched...so on and so forth. Thus although it takes 5 cycles for a single instruction to be completed, pipelining enables a amortized throughput of one instruction per clock.
kayvonf
@landuo: while introductory computer architecture classes typically describe a simple 4- or 5-stage instruction pipeline, the instruction pipeline in modern processors is far more complex. In the heyday of trying to push frequency as high as possible (early 2000's) Intel's pipeline depths got as high as 31 stages (Google Intel's Netburst microarchitecture). A modern Intel processor's pipeline depth is about 14 stages. (This is an example of how today's processors feature multi-core designs with simpler cores, rather than a very complex single core).
Although they get technical quite fast, the articles on Real World Tech are some of the better descriptions of modern architectures. See this one on Intel's Sandy Bridge The intro sums up the processor quite nicely: a 64-bit, quad-core, dual threaded, 4 issue, out-of-order microprocessor with the new 3 and 4 operand AVX instruction set extension, implemented in Intel’s 32nm process. At this point in the course, everyone should know what every term in that sentence means!
Sherry
What does "4 issue" mean? Is it the ILP capability?
kayvonf
The processor can fetch/decode (aka "issue") up to 4 instructions per clock.
What does it mean by that one instruction is executed per clock? Does it mean clock cycle? Because if it means per clock cycle, I'm assuming it's only for this simple example processor, because I learned in 18-240 that each instruction took like 5-6 clock cycles.
@abist. Good question. Yes, I do mean one instruction per clock cycle. In 18-240 you learned that the latency of instructions a small number of clocks, which is true. Modern processors achieve a throughput of one instruction per clock by overlapping execution of several instructions using pipelining (which I won't describe here, but perhaps you discussed it in 240). So for now in the course, it's perfectly reasonable to think of this fictitious processor completing one instruction per clock.
I think there are normally 5 stages of instruction processing within the processor (fetch, decode, execute, memory access and write back), and the processor will fetch one more instruction when the previous one has moved to decoding phase. And when the first fetched instruction go through to execute stage, the second one move on to decode and the third one is fetched...so on and so forth. Thus although it takes 5 cycles for a single instruction to be completed, pipelining enables a amortized throughput of one instruction per clock.
@landuo: while introductory computer architecture classes typically describe a simple 4- or 5-stage instruction pipeline, the instruction pipeline in modern processors is far more complex. In the heyday of trying to push frequency as high as possible (early 2000's) Intel's pipeline depths got as high as 31 stages (Google Intel's Netburst microarchitecture). A modern Intel processor's pipeline depth is about 14 stages. (This is an example of how today's processors feature multi-core designs with simpler cores, rather than a very complex single core).
Although they get technical quite fast, the articles on Real World Tech are some of the better descriptions of modern architectures. See this one on Intel's Sandy Bridge The intro sums up the processor quite nicely: a 64-bit, quad-core, dual threaded, 4 issue, out-of-order microprocessor with the new 3 and 4 operand AVX instruction set extension, implemented in Intel’s 32nm process. At this point in the course, everyone should know what every term in that sentence means!
What does "4 issue" mean? Is it the ILP capability?
The processor can fetch/decode (aka "issue") up to 4 instructions per clock.