Shouldn't BusRd and BusWr at 'Valid' state, lead to flush (writeback to memory)?
cube
I think we're assuming a write-through cache here, so if a processor writes, then it always writes to memory, so we don't have to explicitly show the writing to memory.
kayvonf
@cube: correct.
abist
Sorry, but I don't quite get why we need a BusWr after a PrWr in the Invalid state. If it's invalid anyway, what's the point broadcasting about it?
kayvonf
@abist. The diagram says: if a cache line is in the invalid state, (that is, if the data is not in the cache), then to service a write request to the line from the processor (PrWr) the cache must broadcast this intent to write to the line to all other caches.
Shouldn't
BusRdandBusWrat 'Valid' state, lead to flush (writeback to memory)?I think we're assuming a write-through cache here, so if a processor writes, then it always writes to memory, so we don't have to explicitly show the writing to memory.
@cube: correct.
Sorry, but I don't quite get why we need a BusWr after a PrWr in the Invalid state. If it's invalid anyway, what's the point broadcasting about it?
@abist. The diagram says: if a cache line is in the invalid state, (that is, if the data is not in the cache), then to service a write request to the line from the processor (
PrWr) the cache must broadcast this intent to write to the line to all other caches.Ah that makes sense, thank you!