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byeongcp

Is it correct to assume if a line is in Shared state, no processor has the exclusive write to modify this line (since the line exists in multiple local processor caches and we can only modify a line only if it's exclusive)?

fgomezfr

@byeongcp That's the intent. If one processor wants to write a line, it needs to obtain exclusive access first. As per the previous slide, this would send a read-exclusive transaction to all other processors, which would mark the copies in their caches Invalid. Only after the read-exclusive broadcast completes can the writer edit its copy, which becomes Modified.

kayvonf

@byeongcp: It's more than just "safe to assume" it. That property is an invariant of the MSI protocol that is preserved by its design. Take a look at the protocol state machine on the next slide and see if you can convince yourself that it is in fact impossible for one cache to hold the line the S state while another cache holds the line in the M state.

sgbowen

Is the BusRdX message only generated when a processor is going to write to the line immediately upon receiving it? Or is there any degree to which a processor may try to predict what it wants to do with the line in the future? (For example, if a process sees a read for address X now and a write to address X five instructions later, will it send a BusRdX or a BusRd?)

kayvonf

@sgbowen: Basically what you are describing is a pre-fetch. (Instead of prefetching the data for a line you're suggesting the system prefetch the coherence state.) It's certainly possible a processor might be implemented to do this. However, off the type of my head I do not know if this is a type of speculative operation that current implementations do.