So, incoherent caches seem like a pain. Will we ever run into processors that don't pass up invalidations like this, or have things been done this way pretty much as long as we've had L1 and L2 caches?
rokislt10
It seems like another solution to this would be to use a different eviction policy, one that will always evict the same line for both the L1 and the L2 cache. Are there any systems that solve this problem that way? What kind of applications would not benefit too much from an LRU eviction policy?
cacay
@rbcarlso I don't think there are any singular CPUs that don't maintain coherence for you. When you scale larger, to super computers for example, this type of coherence becomes very expensive. You might start handling coherence at the software level. Here is a relevant paper.
So, incoherent caches seem like a pain. Will we ever run into processors that don't pass up invalidations like this, or have things been done this way pretty much as long as we've had L1 and L2 caches?
It seems like another solution to this would be to use a different eviction policy, one that will always evict the same line for both the L1 and the L2 cache. Are there any systems that solve this problem that way? What kind of applications would not benefit too much from an LRU eviction policy?
@rbcarlso I don't think there are any singular CPUs that don't maintain coherence for you. When you scale larger, to super computers for example, this type of coherence becomes very expensive. You might start handling coherence at the software level. Here is a relevant paper.