How is snooping-based cache implemented in hardware? Is it something like a handler/controller? How stable is it? Would it be error-prone after a long time use?
HingOn
@meatie It seems like the cache controllers do the bus snooping on the interconnect.
How is snooping-based cache implemented in hardware? Is it something like a handler/controller? How stable is it? Would it be error-prone after a long time use?
@meatie It seems like the cache controllers do the bus snooping on the interconnect.
http://www.diva-portal.org/smash/get/diva2:649627/FULLTEXT01.pdf