Previous | Next --- Slide 2 of 45
Back to Lecture Thumbnails

In the event of an atomic read-modify-write that directly preforms the operation on the contents of a line in the L2 cache, does the GPU automatically invalidate the same entry in the L1 cache?


Hmm, given that we don't have cache coherence, it seems unlikely. Because it'd be just like a write, since L1 cache is write-through. So if the atomic op had invalidation, it seems likely that every op would too. But we don't have that.