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If Processor 0 wants to read the blue line, which has the home directory of 1, steps 4 and 5 states that Processor 2 will changes the state of blue line in its cache to shared and updates the presence bit in the home node. My question is, does it update the presence bit to home node (P1) or P0? Here is an inefficiency I thought of if the presence bit was updated to P0.

Assuming after these steps, the blue lines are coherent and reside in caches of P0 and P2 and the memory of P1. It's clear that P0, P1, and P2 have the blue line as shared state so if there was a hypothetical P3 and it wants the blue line, it can get it from any of P0, P1, P2. However, the protocol dictates that P3 will ask the directory in the home node, so if the presence bit was updated to P1, it can just give it to P3 whereas if the presence bit was updated to P0, there will be extra step of P3 asking P0 for the line.


@byeongcp: On this slide, the directory is updated to have presence bits set for P0 and P2, since both of these caches have the line in the shared state. The data from the address highlighted in blue (which physically resides in DRAM located on node 1) is replicated in the caches for P0 and P2. Note that P1's cache does not hold the line, so its presence bit is not set.

In your example, if there was a P3 which needed a copy of the line highlighted in blue, it would need to check the directory first. It cannot "just get the data from P0 or P2" because P3 would not have any knowledge of which caches contained the line. It obtained this information from the directory for the line.


What is the dir revision that the owner node sends to the home node on step 5 along with the data? Is it a message indicating that the data is now shared by processor 2 (previous owner) and processor 0? Basically telling the home node how to update the directory entry?


Yes, I think that's correct. And it clears out the dirty bit in the directory entry for that cache line.


@jazzbass: Yeah. The owner node also needs to tell the home node that it no longer has the cache line in an exclusive (and possibly modifiable) state.