I believe it is because we underallocated the percent of chip for rasterization. We are using 1% of the chip, where we need 1.2% of the chip. Thus, because we underalloacted this by 20%, the other 99% of the chips are idle for the the extra 20% that rasterization will take, which means that are running at 100% - 20% = 80% efficiency.
grose
@Faust Thanks! But I'm not sure I understand the math there.
Suppose we used 1% for rasterizer, but really needed 200% more, i.e. 3% of the chip. Then, rasterization takes 200% more, so according to the equation, we'd be running at 100% - 200% = -100% efficiency, which doesn't sound possible.
yuel1
I believe rather than 80%, the slide should be 1/1.2*100%. Can Kayvon or one of the TAs correct me on this?
Where does the number 80% come from?
I believe it is because we underallocated the percent of chip for rasterization. We are using 1% of the chip, where we need 1.2% of the chip. Thus, because we underalloacted this by 20%, the other 99% of the chips are idle for the the extra 20% that rasterization will take, which means that are running at 100% - 20% = 80% efficiency.
@Faust Thanks! But I'm not sure I understand the math there.
Suppose we used 1% for rasterizer, but really needed 200% more, i.e. 3% of the chip. Then, rasterization takes 200% more, so according to the equation, we'd be running at 100% - 200% = -100% efficiency, which doesn't sound possible.
I believe rather than 80%, the slide should be 1/1.2*100%. Can Kayvon or one of the TAs correct me on this?