One thing that intrigued me during this lecture was a mention of 3-D chips. I briefly looked around and it seems like one of the challenges is the decreased surface area to mass ratio a 3-D chip brings.
But apparently a big research field is using the z-axis to bring memory closer to logical processing to cut energy costs and increase memory bandwidth.
One thing that intrigued me during this lecture was a mention of 3-D chips. I briefly looked around and it seems like one of the challenges is the decreased surface area to mass ratio a 3-D chip brings.
But apparently a big research field is using the z-axis to bring memory closer to logical processing to cut energy costs and increase memory bandwidth.
http://www.gizmag.com/high-rise-3d-chips-big-data/35281/
Slightly off topic. But here's a paper on reconfigurable 3D Network on Chips