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I think it was mentioned that we'd be discussion these models later on, but I don't quite see from the diagram what the difference is between Crossbar and Shared Bus. It seems each is just a different representation of the other.


@jezimmer I could be wrong about this, but if I had to make a best guess given the diagrams... it seems that in the shared bus, there is one hub that each processor / memory unit is connected to and theoretically only one load of information can travel through the bus at once. However, in cross bar, it seems that there is a connection between every entity and the others. (Kayvon mentioned the n^2 number of connections in answering a question on why the crossbar took up so much physical space).


@paluri: correct. (But I'll defer discussion of this to the lecture on interconnected in the second half of the course.)


What factors determine what interconnect they choose to use? Is an n^2 interconnect just the best for general purposes? And can they actually simulate these networks so that they don't have to manufacture them?