The Prescott core has a 31 stages pipeline. Although more stages allow higher throughput and clock rate, too many stages seem to have a bigger heat dissipation problem and an increase in branch misprediction penalty (makes it harder to trace back the stages that went wrong).
kayvonf
Pipelined instruction execution is also another reason why multi-threaded processing is useful. If instructions all come from a single instruction stream, then complex pipeline logic like data forwarding, branch prediction, etc are needed to avoid pipeline stalls in the face of dependencies and data hazards. In a multi-threaded processor, since instructions from different instruction streams are independent, the processor can fill its instruction pipeline by drawing an instruction from different runnable threads each cycle. The result is that the implementation of instruction pipelines can be simpler. (This is another example of removing some of the complex logic present in non-parallel CPUs that we discussed briefly in lecture 2.)
Summary: in a multi-threaded processor, hardware multi-threading is used to hide latency of instruction execution (small latencies) in addition to the large latencies of memory access operations.
http://en.wikipedia.org/wiki/NetBurst_(microarchitecture)
The Prescott core has a 31 stages pipeline. Although more stages allow higher throughput and clock rate, too many stages seem to have a bigger heat dissipation problem and an increase in branch misprediction penalty (makes it harder to trace back the stages that went wrong).
Pipelined instruction execution is also another reason why multi-threaded processing is useful. If instructions all come from a single instruction stream, then complex pipeline logic like data forwarding, branch prediction, etc are needed to avoid pipeline stalls in the face of dependencies and data hazards. In a multi-threaded processor, since instructions from different instruction streams are independent, the processor can fill its instruction pipeline by drawing an instruction from different runnable threads each cycle. The result is that the implementation of instruction pipelines can be simpler. (This is another example of removing some of the complex logic present in non-parallel CPUs that we discussed briefly in lecture 2.)
Summary: in a multi-threaded processor, hardware multi-threading is used to hide latency of instruction execution (small latencies) in addition to the large latencies of memory access operations.