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Kapteyn

Since option 1 assumes all caches will respond in a fixed number of cycles, is it correct to say that an option 1 implementation would not need a snoop valid line?

Also, I think having duplicate tags is not the only requirement to ensure that caches will respond with snoop results in a fixed number of clock cycles.

Say we want to guarantee that caches will respond within 3 cycles to a bus request and that it takes 1 cycle for the cache to do the necessary tag checking to send off a snoop response.

It seems we would also need to implement a cache that will give priority to servicing snoop requests instead of processor requests once 2 cycles have passed. This is because we could have a situation where the processor wants to update a tag on the third cycle while the snoop side needs to read that tag to send off the correct snoop response. So the snoop side has to be able to lock out the processor side to do its task within 3 cycles.

kayvonf

@Kapteyn: Good! These are all important issues that a real chip architect would have to address.

sanchuah

Does option 2 mean that memory will not respond until snoop_valid turn 0?

parallelfifths

@sanchuah, yes, I believe that's correct, because the change in the snoop_valid line is the signal that all caches have had an opportunity to report their results and it is okay to read the values of the "shared" and "dirty" lines.

ekr

@Kapetyn I would say yes, option 1 would not need a snoop valid line. However, we would probably still want one, because this option only sets an upper bound on the amount of time to respond. If all processors respond in a much shorter time, it would be a waste to wait the remaining duration even though the response is complete.