I talked about this on a previous slide, but for AMD's cache controller reference manual, they also provide their own timing diagrams for a single read miss transaction
On slide 28, the global order that writes appear on the atomic bus is what ensures write serialization. On the split-transaction bus, is the order that writes appear on the request bus the global ordering, since it is where all caches acknowledge the snoop result?
I talked about this on a previous slide, but for AMD's cache controller reference manual, they also provide their own timing diagrams for a single read miss transaction
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0329l/BABJIFEC.html#BABDEFCI
On slide 28, the global order that writes appear on the atomic bus is what ensures write serialization. On the split-transaction bus, is the order that writes appear on the request bus the global ordering, since it is where all caches acknowledge the snoop result?