A great exercise is to look through this sequence of slides describing a basic hardware implementation of lazy, optimistic transactional memory and then describe all the changes that are necessary (CPU state and also cache logic) on top a basic invalidation-based cache coherence protocol.
A great exercise is to look through this sequence of slides describing a basic hardware implementation of lazy, optimistic transactional memory and then describe all the changes that are necessary (CPU state and also cache logic) on top a basic invalidation-based cache coherence protocol.