As said in class L1/2 caches are specific to each processor while the L3 cache sits in between the interconnect and memory.
totofufu
What does the interconnect exactly do that the L3 cache doesn't? The L3 cache keeps track of any pieces of memory that must be loaded or stored between all the processors and main memory - it essentially acts as a communicator between the two. So what extra information does the interconnect carry? Does it just keep track of cache misses for each processor and communicate this info to the other processors?
hofstee
@totofufu the interconnect is responsible for all communication between cores. The L3 cache is just a cache. The interconnect is what is responsible for allowing the cores to communicate with the cache, with eachother, the on chip gpu, and maintaining cache coherence.
418_touhenying
Then if the shared cache (such as L3) were to be drawn here, would it stay in the same place as the interconnect?
hofstee
@418_touhenying not necessarily. If you were looking at this diagram as each processor being a core, you would consider the L3 to be where the Memory label is. If you consider the Memory label to be the more traditional DRAM, then the L3 would be in the local cache.
Perhaps I was a bit vague in my answer. In reality there is an interconnect between each core in the middle of the L2 and L3 caches, as well as there being an interconnect between two sockets on a motherboard, etc. At any point where the memory hierarchy divides itself between multiple compute elements, you will probably find an interconnect.
As said in class L1/2 caches are specific to each processor while the L3 cache sits in between the interconnect and memory.
What does the interconnect exactly do that the L3 cache doesn't? The L3 cache keeps track of any pieces of memory that must be loaded or stored between all the processors and main memory - it essentially acts as a communicator between the two. So what extra information does the interconnect carry? Does it just keep track of cache misses for each processor and communicate this info to the other processors?
@totofufu the interconnect is responsible for all communication between cores. The L3 cache is just a cache. The interconnect is what is responsible for allowing the cores to communicate with the cache, with eachother, the on chip gpu, and maintaining cache coherence.
Then if the shared cache (such as L3) were to be drawn here, would it stay in the same place as the interconnect?
@418_touhenying not necessarily. If you were looking at this diagram as each processor being a core, you would consider the L3 to be where the Memory label is. If you consider the Memory label to be the more traditional DRAM, then the L3 would be in the local cache.
Perhaps I was a bit vague in my answer. In reality there is an interconnect between each core in the middle of the L2 and L3 caches, as well as there being an interconnect between two sockets on a motherboard, etc. At any point where the memory hierarchy divides itself between multiple compute elements, you will probably find an interconnect.