Is it true that for all the DRAMS in the world, there is only one active row?
hofstee
To add to this slide, DRAM is made of capacitors (water bucket). There is no such thing as a perfect capacitor (the water bucket leaks). This means that every so often, you need to refresh the charge in every single row of your DIMM, adding even more to the latency (and power! even when you're not doing anything at all!).
mallocanswer
@pavelkang, I think it is meaningless to have two or more active rows at a time under today's DRAM structure because you only have one row buffer.
rmanne
In other news, there are alternatives to DRAM where this refresh doesn't need to be made. This includes SRAM, 'static RAM', which is significantly more expensive, so it would be too costly to implement for main memory, but is also significantly faster, and apparently it's used in CPU caches (which, in combination with their reduced size, can achieve well over 3x the bandwidth).
hofstee
@rmanne to add context, transfer speeds with SRAM can be on the order of terabytes per second.
CaptainBlueBear
@pavelkang according to this link posted on the previous slide, modern DRAMs are split into multiple equal-sized units called banks (a DRAM having 8 to 16 banks) and each of those banks can be accessed in parallel access (so a DRAM can have as many active rows as the number of banks it has)
thomasts
(Unrelated to previous posts---) On the slides, the first question is "when to execute precharge?" The answer sort of depends on the pattern of data access. If there's locality in data accesses, it would be better to be lazy about flushing out the row buffer since data can often be read out of the current active row without any flushing. But if there isn't much locality, then it's better to flush as soon as possible so that this extra step of flushing doesn't sit in the critical path of row-fetching.
a
I just wanted to point out that these latency timings aren't veiled or hidden internal specifications -- when shopping for RAM, you can actually comparison-shop based on these latency timings. For example, 9-9-9-24 in this product's title corresponds to CAS-RCD-RP-RAS latencies, in cycles.
Richard
So each precharge is charging all the rows? Will this consume much more time than a row activation or column access?
hofstee
The precharge just writes the current active row back into the DIMMs, and then applies a voltage to the row we want so there is sufficient voltage for the sense amplifier to correctly function. This is just a matter of a few transistors being switched so precharging a specific row is probably combinational logic. But since we need to also write the previous row back, this adds to the time. For most consumer RAM, precharge, CAS latency, and row to column delay are around the same time.
Is it true that for all the DRAMS in the world, there is only one active row?
To add to this slide, DRAM is made of capacitors (water bucket). There is no such thing as a perfect capacitor (the water bucket leaks). This means that every so often, you need to refresh the charge in every single row of your DIMM, adding even more to the latency (and power! even when you're not doing anything at all!).
@pavelkang, I think it is meaningless to have two or more active rows at a time under today's DRAM structure because you only have one row buffer.
In other news, there are alternatives to DRAM where this refresh doesn't need to be made. This includes SRAM, 'static RAM', which is significantly more expensive, so it would be too costly to implement for main memory, but is also significantly faster, and apparently it's used in CPU caches (which, in combination with their reduced size, can achieve well over 3x the bandwidth).
@rmanne to add context, transfer speeds with SRAM can be on the order of terabytes per second.
@pavelkang according to this link posted on the previous slide, modern DRAMs are split into multiple equal-sized units called banks (a DRAM having 8 to 16 banks) and each of those banks can be accessed in parallel access (so a DRAM can have as many active rows as the number of banks it has)
(Unrelated to previous posts---) On the slides, the first question is "when to execute precharge?" The answer sort of depends on the pattern of data access. If there's locality in data accesses, it would be better to be lazy about flushing out the row buffer since data can often be read out of the current active row without any flushing. But if there isn't much locality, then it's better to flush as soon as possible so that this extra step of flushing doesn't sit in the critical path of row-fetching.
I just wanted to point out that these latency timings aren't veiled or hidden internal specifications -- when shopping for RAM, you can actually comparison-shop based on these latency timings. For example, 9-9-9-24 in this product's title corresponds to CAS-RCD-RP-RAS latencies, in cycles.
So each precharge is charging all the rows? Will this consume much more time than a row activation or column access?
The precharge just writes the current active row back into the DIMMs, and then applies a voltage to the row we want so there is sufficient voltage for the sense amplifier to correctly function. This is just a matter of a few transistors being switched so precharging a specific row is probably combinational logic. But since we need to also write the previous row back, this adds to the time. For most consumer RAM, precharge, CAS latency, and row to column delay are around the same time.