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Physical address corresponding to a cache line should be arranged properly to lower the latency of access. For example, they maybe arranged in a single row so there won't be unnecessary pre-charge and row activation.


Why is it bad that the pins are used a small fraction of the time? If they are the scarcest resource, isn't it good that they aren't in high demand so there wouldn't be contention?


@huehue, data is transmitted through the pins. If we can keep pins busy all the time, we can maximize the memory throughput.


Why can't we pipeline this operation by executing the precharge for access 3 while the cas is active for access 2? Wouldn't that increase performance?


@chuangxuean to do that we would need a extra row buffer which would precharge and store next row while the first row is being served. I am not EEE guy and so dont know how feasible it is to implement but I think that would help in reducing latency.