Since the cache line is 512 bits, would we need to activate a second row to get all of the bytes? Because using just the current row, wouldn't we only be able to get 256 of the bits?
In order to get a higher effective bandwidth (384 bit or 512 bit memory bus bandwidth), we would need to have multiple DIMMs that can be accessed in parallel, which would further complicate how we distribute physical addresses across the system.
MuscleNerd
Also mentioned in lecture was something about each chip working in 'BURST' mode. In this case, how would the memory be arranged. Contiguous memory would be like a concatenation of the same row on all chips?
Since the cache line is 512 bits, would we need to activate a second row to get all of the bytes? Because using just the current row, wouldn't we only be able to get 256 of the bits?
I think each row has 2KBits, right? Slide 10
In order to get a higher effective bandwidth (384 bit or 512 bit memory bus bandwidth), we would need to have multiple DIMMs that can be accessed in parallel, which would further complicate how we distribute physical addresses across the system.
Also mentioned in lecture was something about each chip working in 'BURST' mode. In this case, how would the memory be arranged. Contiguous memory would be like a concatenation of the same row on all chips?