What happens if you store 0-63 on chip 1, 64-127 on chip 2, etc. Then reading 512 bits takes the same time (8 cycles). But you have to coalesce reads differently.
teamG
@lol, think this is what Kayvon mentioned in lecture. However, if we want to achieve the same throughput with this setup, we would need to transfer memory using burst mode. Also, the main difference is that if one wants the first word in the cache line faster(in other words, the first 64 bits). The scheme used in the slide would be better because we would be able to get the entire first word after one cycle. With burst mode, we won't be able to achieve that in 1 cycle.
What happens if you store 0-63 on chip 1, 64-127 on chip 2, etc. Then reading 512 bits takes the same time (8 cycles). But you have to coalesce reads differently.
@lol, think this is what Kayvon mentioned in lecture. However, if we want to achieve the same throughput with this setup, we would need to transfer memory using burst mode. Also, the main difference is that if one wants the first word in the cache line faster(in other words, the first 64 bits). The scheme used in the slide would be better because we would be able to get the entire first word after one cycle. With burst mode, we won't be able to achieve that in 1 cycle.