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Can someone please explain how 3D stacking of chips reduces power? What is the difference between stacking chips versus laying them out side-by-side?


@anonymous Perhaps by stacking the chips closer, it reduces the latency of travel of information between the chips, thereby reduces the overall power usage for transport.


I think that for some fixed frequency, the power consumed by a chip increases as the area of it increases.


One benefit is that, by stacking, interconnect wires get shorter and thus would reduce the stray capacitance, which is unavoidable yet undesired. An electronic component would have capacitance with another one close to it and as wires get closer to each other this effect would get more phenomenal


I think why it reduces power is that all DRAMs can be powered under same control, which can bring up some optimization.