I'm confused about cores and processors being used interchangeably in the lecture. As far as I know, L1 caches are private to each core, L2 caches are shared among cores but private to each processor and L3 caches are shared among processors in a multi-core, multi-processor environment. Can someone expand on the above slide with respect to both cores and processors in the said environment?
The terms core and processor seem to be used synonymously in this lecture. For example, the processors in slides 6-8 refer to the same thing as the cores in this slide.
So, the diagram shows that the L1 and L2 caches are private to each core/processor, whereas the L3 is shared among all of the cores/processors.
What is the "bank" per core and what does it provide?
How much relative space do cache controllers take up on a normal modern CPU?
The bank is a unit of memory that allows the memory to recover between separate requests, and allows for a reduction of bank cycle time:
Is this similar to memory banks (shared memory) on a GPU, which can be accessed in parallel? The L3 cache has 4 banks, so does this mean the total bandwidth to L3 is 4 times the bus bandwidth?
As I was doing research about shared cache, one of the earliest CPUs that implemented both shared cache and a private cache for each core is the is the Intel Core Duo series. However, that series of processors had a shared cache in L2. Looking at this architecture, seems like the trend is to push shared caches to higher levels??