Examples could be transferring data from an external disk to memory, or network data to memory, etc. Essentially DMA is used to allow IO to read and write to memory without using the CPU. So you can see the provlem where the CPU and IO independently have access to memory creates for cache coherence. Suppose the CPU reads a value and puts it in the cache. Then suppose DMA reads the same address. There has to be logic which flushes the cache before DMA can perform a read. Similarly, if DMA writes to memory which is also in CPU cache, then the cacheline must be invalidated.
Could someone give an example of DMA?
Examples could be transferring data from an external disk to memory, or network data to memory, etc. Essentially DMA is used to allow IO to read and write to memory without using the CPU. So you can see the provlem where the CPU and IO independently have access to memory creates for cache coherence. Suppose the CPU reads a value and puts it in the cache. Then suppose DMA reads the same address. There has to be logic which flushes the cache before DMA can perform a read. Similarly, if DMA writes to memory which is also in CPU cache, then the cacheline must be invalidated.