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A little confused about the diagram. When it is in the valid state, why BusWr still leads to valid state? Shouldn't it be changed to invalid since it is broadcasted from other processors?


... Never mind. Didn't notice the note: A/B if event A observed by cache controller, the naction B is taken.


If this cache is write-allocate cache, when the cache is invalid, and there comes PrWr, then the cache state will become Valid. Is this right?


@momoda I think it is right, as the data will be loaded into the cache first.


The BusRd messages don't seem to do anything in this diagram. What's the purpose of sending those messages out?

EDIT: They have a purpose in the protocol described on slide 28, but not this one.


Does bus read getting data from remote caches generally mean "from main memory"?


Based of my understanding of the A/B notation, I am confused on why when it is in the invalid state, and a PrWr is observed by the cache controller, does a BusWr action have to be taken?


@ote If a the controller observes a write, it is important that we move all caches that are in valid state to invalid state (the blue line). I think the confusing part about this scheme is that we are allowed to write to a cache line WITHOUT having the most-recent updated values of that line.


Kayvon said "If the processor writes, it will just write to memory without bringing in the line". So if the processor is in Invalid, i.e. nothing in the cache line or stale data in the cache line, will it overwrite the data in memory with stale data? If not, and the processor does nothing for that PrWr, why is broadcasting BusWr necessary at all?


If using write-allocate policy, when the processor is in invalid state and wants to write, it should first perform a read and becomes valid state. Then it performs a write so it should stay in valid state.


@monkeyking, the slide says "**Assume write no-allocate policy".


Does the notation PrRd/BusRd means: If I am in invalid state and my processor reads, I have to send a message to the bus and tell other processor to read?


@cyl, I think it means that in invalid state when the processor want to read, the bus will have to read from main memory.


@xingdaz, suppose we want to write 1 to X and X is not in the local cache. So the processor is in invalid state. However, when the processor writes 1 to X, it needs to notify other processors because they may have a local copy in their caches.