Kinda confused. But let me explain what I think, when any processor writes to shared memory, all other processors are notified, and an invalidation is applied to ensure no other processor do not write to the shared memory while another processor is writing to it.
Is that what the diagram means?
arcticx
@Funky9000 Yes, I think you are right.
hofstee
@Funky9000 not only write, but also for reads. If it didn't invalidate even if we didn't intend to write, the data we would read would be stale.
kayvonf
I'd like to suggest that we more precisely say "write to address X in the address space" rather than "shared memory".
In this simple coherence protocol, when a process performs a write to address X, the all other caches in the system invalidate their copy of the line containing X (if a valid copy exists).
msfernan
Just clarifying. When the cache controller for Processor A, observes a read by Procesor A it issues a BusRd that gets the data from memory and sends the cache of Processor A to valid state. Or is BusRd obtaining the value from the cache of another processor before sending Processor A to valid state?
kayvonf
@msfernan. Either solution is a valid protocol. MOESI and MESIF are two more complicated protocols that define switch cache provides the data when multiple caches have it.
Kinda confused. But let me explain what I think, when any processor writes to shared memory, all other processors are notified, and an invalidation is applied to ensure no other processor do not write to the shared memory while another processor is writing to it.
Is that what the diagram means?
@Funky9000 Yes, I think you are right.
@Funky9000 not only write, but also for reads. If it didn't invalidate even if we didn't intend to write, the data we would read would be stale.
I'd like to suggest that we more precisely say "write to address X in the address space" rather than "shared memory".
In this simple coherence protocol, when a process performs a write to address X, the all other caches in the system invalidate their copy of the line containing X (if a valid copy exists).
Just clarifying. When the cache controller for Processor A, observes a read by Procesor A it issues a BusRd that gets the data from memory and sends the cache of Processor A to valid state. Or is BusRd obtaining the value from the cache of another processor before sending Processor A to valid state?
@msfernan. Either solution is a valid protocol. MOESI and MESIF are two more complicated protocols that define switch cache provides the data when multiple caches have it.