Previous | Next --- Slide 33 of 56
Back to Lecture Thumbnails



What does 'application has no sharing' mean? Why would a processor load this cache line and not do anything about it?


@pavelkang I guess 'application has no sharing' means that in MSI it can be the case where a cache line L is invalid and L is the only copy in the cache for processor P0. If in the future P0 wants to write to L, it has to issue an interconnect transaction to move from I state to M state. This is extremely inefficient considering that this cache line is only resident in P0's cache. P0 could have written directly to this cache line.

This situation can happen. Imagine that initially many processors, including P0, has L in cache. At some point in time, the copy of L in P1's cache may be modified by P1. This invalidates all other copies of L in other processors' caches. Furthermore, when all processors but P0 think they won't use L any more, they will evict L out of their caches, which gives the situation where only P0 has an invalid copy of L in its cache.

The above thought is based on my understanding of the lecture so far. Please correct me if any part of my presentation is flawed.


@haboric I thought invalidating a line was equivalent to dropping/evicting it from the cache. From what you're saying, it sounds like an invalidated line can stay in the cache but is just marked as invalid somehow. Can somehow confirm which is true?


Imagine the following sequence of instructions:

ld  X, R0
add R0, R0, 5   # x += 5
st  X, R0

In this sequence, the processor issues a load instruction to bring a value X into a register. Then adds 5 to the register, and then stores the updated contents out to memory.

The original load, if it was a cache miss, would load data from memory and allocate the line containing X in the case. Since this operation was a read, in the MSI protocol it would be loaded in the S state.

Now, in this case, the later store would ALSO be a "coherence miss", since the store needs the line in the M state (and it is only in the S state). As a result, according to the MSI protocol, the cache would need to inform all the other processors of the intent to write by broadcasting BusRdX (In practice it would actually broadcast a "bus upgrade" request, since there's no need to actually reload the line from memory.)

This second coherence broadcast is unnecessary if there are no sharers of the line containing X. Therefore, the MESI protocol adds an additional state to MSI to differentiate between 'S' ("shared": in cache, no write permissions, may also be in other caches) and E ("exclusive clean": in cache, no write permissions, but not in any other caches).