Previous | Next --- Slide 54 of 56
Back to Lecture Thumbnails
Lawliet

In general, it seems like at a certain point, the amount of false sharing that occurs increases more than the amount of true sharing or other cache problems decrease. Does this mean that there exists some optimal cache line size or is it just because we didn't optimize the program to fit with the larger cache lines?

acfeng

I understand what false sharing and true sharing is, but what does "Upgrade" mean in respect to cache line misses?

kayvonf

@acfeng. "Upgrade" is the S-to-M state transition in MSI or MESI. It's considered a coherence miss (aka a communication miss) since even though the line is in cache, the cache has to make a coherence message broadcast to move the line to the M state.

pkoenig10

@Lawliet. I would assume it is a little bit of both. Larger cache line sizes inherently mean more false sharing because each cache line contains more data. We likely could have optimized these programs to fit with larger cache lines by making larger parallel chunks, etc. However our ability to optmize these programs will be limited by 1) the size of our cache and 2) the memory bandwidth (larger cache lines == need larger cache/memory bandwidth to load and hold larger chunks per parallel task).