Why does the data from the miss from the processor on the left not come from main memory? Is that due to an assumption that the data that it wants to read is a dirty line in processor on the right and hence it has to fetch data from it?
illuminated
@chuangxuean Even if it is not dirty we're assuming that the processor on the left sends a snoop on the bus and finds a nearby cache is holding the data. This would likely be faster than immediately deferring to main memory (I'm not sure exactly how this type of choice would be implemented though).
Why does the data from the miss from the processor on the left not come from main memory? Is that due to an assumption that the data that it wants to read is a dirty line in processor on the right and hence it has to fetch data from it?
@chuangxuean Even if it is not dirty we're assuming that the processor on the left sends a snoop on the bus and finds a nearby cache is holding the data. This would likely be faster than immediately deferring to main memory (I'm not sure exactly how this type of choice would be implemented though).