It is interesting to note that in commercial chips like the one here, even though there may be the possibility of ILP just by looking at the assembly, the processor may not be able to take advantage of it because unlike the abstraction presented in this lecture with multiple execution blocks, a single core with an execution unit as shown above cannot perform 2 floating point instructions even if there are no dependencies in the instructions themselves and they use different floating point registers because there's only one copy of the FPU in the execution unit. On the other hand, this processor could perform 2 integer ops simultaneously if they were independent of each other
It is interesting to note that in commercial chips like the one here, even though there may be the possibility of ILP just by looking at the assembly, the processor may not be able to take advantage of it because unlike the abstraction presented in this lecture with multiple execution blocks, a single core with an execution unit as shown above cannot perform 2 floating point instructions even if there are no dependencies in the instructions themselves and they use different floating point registers because there's only one copy of the FPU in the execution unit. On the other hand, this processor could perform 2 integer ops simultaneously if they were independent of each other
Good comment @kapalani.