Question: based on the description, which kind of multi-threading do we support here? temporal or simultaneous?
@doodooloo This chip supports temporal (Interleaved) multi-threading because when one instruction stream stalls, a core can switch to the other execution context and continue running.
What I'm not quite sure about is the simultaneous multi-threading because the description says that each core can execute up to two instructions per clock from one instruction stream, but I believe that simultaneous multi-threading should require each core to be able to run instructions simultaneously from 2 or more threads and not be limited to a single thread/instruction stream.
@Firephinx You are right. Based on the description, we only have temporal multi-threading. And in order to support SMT, a core must be able to execute multiple instructions from multiple instructions streams.
The slide states that each core in this illustration can execute one SIMD instruction + one scalar instruction at a time.
Could the SIMD Exec block be used as a standard Exec block, in order to run two scalar instructions instead of one scalar and one SIMD?
Asking because I can't think of a reason this wouldn't work, but I don't think we addressed it.
It seems to me that you can, but I'd appreciate it if someone more knowledgeable than I am weighed in.
When it says, "when faced with a stall," it's talking about memory latency, right? Is there another kind of stall that would warrant switching instruction streams?