The reason why DMA is an exception in uniprocessor is that DMA will access memory via bus ignoring the value in cache.
For example, variable X is read and updated by a processor and the updated value is now cached, so the value in memory and cache is not consistency (write back mechanism). If DMA wants to read variable X from memory, it cannot get the "last" value. The common method is to manually flush cache before using DMA to access the data.
Similarly, if a device updates a variable Y via DMA, and the variable Y is cached in the processor (because variable Y is used before and still exists in the cache, write back mechanism). At this time, if the processor wants to use the "last" value, it has to invalid that cache line, and reads the correct version of Y value from memory.
ctabrizi
A good followup question would be: to what extent is it appropriate to think of other devices in this context (devices interacting via DMA) as imposing the same requirements as the processor having an additional core?
The reason why DMA is an exception in uniprocessor is that DMA will access memory via bus ignoring the value in cache.
For example, variable X is read and updated by a processor and the updated value is now cached, so the value in memory and cache is not consistency (write back mechanism). If DMA wants to read variable X from memory, it cannot get the "last" value. The common method is to manually flush cache before using DMA to access the data.
Similarly, if a device updates a variable Y via DMA, and the variable Y is cached in the processor (because variable Y is used before and still exists in the cache, write back mechanism). At this time, if the processor wants to use the "last" value, it has to invalid that cache line, and reads the correct version of Y value from memory.
A good followup question would be: to what extent is it appropriate to think of other devices in this context (devices interacting via DMA) as imposing the same requirements as the processor having an additional core?