If it's write allocate policy, when the processor writes (PrWr) on a invalid status, it issues a BusWr, and change the status from invalid to valid.
Levy
In the scenario BusRd is actually of no use, is that correct?
rrp123
@levy BusRd just lets all the other processors know who has a copy of the cache line, which in this scenario isn't used. But it is later in the MESI protocol as well as directory based coherency.
ykt
It is true that other processors do not need to know that you want to load a cache line, but the memory still needs to know the request to be able to service it. Hence, the BusRd message. Also, in some implementations, if the line is already present in another processor's cache, then that processor's cache might be able to provide the data (avoids having to go to memory).
If it's write allocate policy, when the processor writes (PrWr) on a invalid status, it issues a BusWr, and change the status from invalid to valid.
In the scenario BusRd is actually of no use, is that correct?
@levy BusRd just lets all the other processors know who has a copy of the cache line, which in this scenario isn't used. But it is later in the MESI protocol as well as directory based coherency.
It is true that other processors do not need to know that you want to load a cache line, but the memory still needs to know the request to be able to service it. Hence, the BusRd message. Also, in some implementations, if the line is already present in another processor's cache, then that processor's cache might be able to provide the data (avoids having to go to memory).