If two processors write at the same time, whoever broadcasts BusWr message first wins and the other processor will receive the BusWr signal and move to Invalid state and do PrWr there.
slowloris
I think there may be something wrong with the diagram.
Since we are assuming a write no-allocate policy (as is specified in the left-bottom corner), if processor P writes to X, P should invalidate the cache line of X.
The diagram correctly shows that P invalidates its cache line of X when it receives a BusWr from a transaction that P did not initiate (the blue arrow). However, in the case where P initiates (as specified by the black text) the write to X (and receives a BusWr as a result), we see that no invalidation takes place in P's cache. However, this should be incorrect because, according to the write no-allocate policy, P's cache should not have been updated by P's write to X (only memory should have been updated). Therefore, P's cache line of X should go to the invalid state.
Can somebody please confirm or deny this?
kayvonf
@slowloris. The diagram is correct. It is a write through policy, and write-through no allocate means if the line is not in the cache it doesn't get brought into the cache on a write. (Stay in the I state.). However, if the line is in the cache at the time of the write, the write will go out to memory (it's write through) but the line will remain in cache. (Stay in V state.) There would be no reason to invalidate a line that's already sitting there in cache, since there might soon be a read to that line.
If two processors write at the same time, whoever broadcasts BusWr message first wins and the other processor will receive the BusWr signal and move to Invalid state and do PrWr there.
I think there may be something wrong with the diagram.
Since we are assuming a write no-allocate policy (as is specified in the left-bottom corner), if processor P writes to X, P should invalidate the cache line of X.
The diagram correctly shows that P invalidates its cache line of X when it receives a BusWr from a transaction that P did not initiate (the blue arrow). However, in the case where P initiates (as specified by the black text) the write to X (and receives a BusWr as a result), we see that no invalidation takes place in P's cache. However, this should be incorrect because, according to the write no-allocate policy, P's cache should not have been updated by P's write to X (only memory should have been updated). Therefore, P's cache line of X should go to the invalid state.
Can somebody please confirm or deny this?
@slowloris. The diagram is correct. It is a write through policy, and write-through no allocate means if the line is not in the cache it doesn't get brought into the cache on a write. (Stay in the I state.). However, if the line is in the cache at the time of the write, the write will go out to memory (it's write through) but the line will remain in cache. (Stay in V state.) There would be no reason to invalidate a line that's already sitting there in cache, since there might soon be a read to that line.
@kayvonf gotcha. Thank you