A bit suggestion on this example: instead of giving one paper to a student once he requests the memory, we can give he a set of paper for the same memory (e.g. X=1, X=2, X3) so he can update the value by himself (that is what the processor do).
emt
This exercise illustrated that the actual design of the cache facilitates these types of transactions; it's not facilitated by the software. Additionally, anything that changes the state of the cache will be communicated to the other processors, while anything that does not change the state won't need to be told to other processors.
harlenVII
Please note that the state is for each cache line! Different cache line can have different state.
A bit suggestion on this example: instead of giving one paper to a student once he requests the memory, we can give he a set of paper for the same memory (e.g. X=1, X=2, X3) so he can update the value by himself (that is what the processor do).
This exercise illustrated that the actual design of the cache facilitates these types of transactions; it's not facilitated by the software. Additionally, anything that changes the state of the cache will be communicated to the other processors, while anything that does not change the state won't need to be told to other processors.
Please note that the state is for each cache line! Different cache line can have different state.