Is it right to assume that both L1 and L2 cache of the same processor will always be in the same state (M/E/S/I)?
pdp
@nemo: There will be some cache lines which are present in L2 and will not be present in L1 (as L1 is a subset of L2). So, BusRd and BusRdX will cause L2 to be in a specific state. I don't know if it will propagate those states to L1 as well if "in L1 bit" is not set.
anonymous
@nemo I think the state (M/E/S/I) is binded to a certain variable, so the cache doesn't need to be in the same state. Here, the mechanism just makes sure that L1 is always a subset of L2, and for those variables in L1, they will share the same state.
That's my understanding, correct me if there's some error.
eosofsky
@anonymous - It's not that the M/E/S/I state is binded to a certain variable, but rather a certain cache line.
Is it right to assume that both L1 and L2 cache of the same processor will always be in the same state (M/E/S/I)?
@nemo: There will be some cache lines which are present in L2 and will not be present in L1 (as L1 is a subset of L2). So, BusRd and BusRdX will cause L2 to be in a specific state. I don't know if it will propagate those states to L1 as well if "in L1 bit" is not set.
@nemo I think the state (M/E/S/I) is binded to a certain variable, so the cache doesn't need to be in the same state. Here, the mechanism just makes sure that L1 is always a subset of L2, and for those variables in L1, they will share the same state.
That's my understanding, correct me if there's some error.
@anonymous - It's not that the M/E/S/I state is binded to a certain variable, but rather a certain cache line.