In this case, P1 may reorder A=1, flag =1 , and the output 0 can also be printed. This is not possible in TSO or PC.
Metalbird
By allowing more of these relaxations, we are able to execute our code faster, however, care has to be taken to ensure that the results are sequentially consistent. As mentioned above, in this program if we allowed for the relaxation where writes can be reordered, we would have to ensure that the relaxation would not produce wrong results in our code. Mechanisms such as locks, or other tricks would have to be used in cases where there are dependencies between processors to ensure sequential consistency.
shpeefps
I'm assuming that even when W->W order is relaxed, the writes to the same address still maintain order. Can anyone confirm?
In this case, P1 may reorder A=1, flag =1 , and the output 0 can also be printed. This is not possible in TSO or PC.
By allowing more of these relaxations, we are able to execute our code faster, however, care has to be taken to ensure that the results are sequentially consistent. As mentioned above, in this program if we allowed for the relaxation where writes can be reordered, we would have to ensure that the relaxation would not produce wrong results in our code. Mechanisms such as locks, or other tricks would have to be used in cases where there are dependencies between processors to ensure sequential consistency.
I'm assuming that even when W->W order is relaxed, the writes to the same address still maintain order. Can anyone confirm?