The third bullet is important to remember. See my comment on slide 17.
bharadwaj
I'm unconvinced that R-->W and W-->W reorderings maintain program correctness. How are we assured that such a reordering doesn't change program behavior?
Also, I'm assuming all of this happens on a program that runs on more than one processor. That is, when we say W-->W, the two writes don't necessarily happen on the same processor.
jmc
@bharadwaj, see my comment on slide 17. This confused me too. I believe all these orderings are with respect to one processor's instructions. Suppose you had only a single processor. Exploiting ILP in this context would just require reordering instructions (reads, writes, arithmetic, whatever) only in a way that results in the same final state as if they were executed in original order. However, in the multi-processor context, that's when we run into the problem of memory consistency, because even if the final state (of memory) is not affected by the way processor 1 reorders its instructions, the intermediate states may be different, and the concurrently executing processors 2, 3, etc. will interact with these changed intermediate states, resulting in a different behavior. See also my chart on slide 21.
Levy
@bharadwaj, the reordering does make a programming running on multicores do nondeterministic behaviors. But if only one threads are used, or the threads do not interact with each other in such a subtle way (e.g. most applications), it is okay. But when it comes to implementing OS, etc., it is lethal to omit such uncertainty.
whitelez
Please correct me if I am wrong, All R->W, W->W, and W->R reordering should not be modify or update the same address under one instruction stream. The correct order would not be preserved these instructions are performing on the same single variable
life
In the era when processors have only one core, compilers and CPUs do out-of-order optimizations to programs in order for better performance. However, when more cores are added to CPUs, out-of-order executions of individual cores cause trouble as it does not guarantee the consistency of intermediate results. Memory consistency model helps to maintain (to some extent) the consistency of intermediate results.
shpeefps
Say in multi-processor context we had threads that interact with each other's modification of memory. Is there a way to determine if our program will behave as expected with the relaxed memory constraints without actually implementing the program? That is, is there a set of invariants you can look at to determine if your program would work in such a machine?
The third bullet is important to remember. See my comment on slide 17.
I'm unconvinced that R-->W and W-->W reorderings maintain program correctness. How are we assured that such a reordering doesn't change program behavior?
Also, I'm assuming all of this happens on a program that runs on more than one processor. That is, when we say W-->W, the two writes don't necessarily happen on the same processor.
@bharadwaj, see my comment on slide 17. This confused me too. I believe all these orderings are with respect to one processor's instructions. Suppose you had only a single processor. Exploiting ILP in this context would just require reordering instructions (reads, writes, arithmetic, whatever) only in a way that results in the same final state as if they were executed in original order. However, in the multi-processor context, that's when we run into the problem of memory consistency, because even if the final state (of memory) is not affected by the way processor 1 reorders its instructions, the intermediate states may be different, and the concurrently executing processors 2, 3, etc. will interact with these changed intermediate states, resulting in a different behavior. See also my chart on slide 21.
@bharadwaj, the reordering does make a programming running on multicores do nondeterministic behaviors. But if only one threads are used, or the threads do not interact with each other in such a subtle way (e.g. most applications), it is okay. But when it comes to implementing OS, etc., it is lethal to omit such uncertainty.
Please correct me if I am wrong, All R->W, W->W, and W->R reordering should not be modify or update the same address under one instruction stream. The correct order would not be preserved these instructions are performing on the same single variable
In the era when processors have only one core, compilers and CPUs do out-of-order optimizations to programs in order for better performance. However, when more cores are added to CPUs, out-of-order executions of individual cores cause trouble as it does not guarantee the consistency of intermediate results. Memory consistency model helps to maintain (to some extent) the consistency of intermediate results.
Say in multi-processor context we had threads that interact with each other's modification of memory. Is there a way to determine if our program will behave as expected with the relaxed memory constraints without actually implementing the program? That is, is there a set of invariants you can look at to determine if your program would work in such a machine?