Why hierarchical snooping helps? Let me try to explain this, please correct me if wrong.
If the right group sends a BusRdX message to the left group, and no processors of left group is in S or M state, then nothing needs to be further broadcast to the left group, potentially saving half broadcast.
However there are cases where the broadcast can't be saved. for example if right group sends BusRdX, and some processor in left group is actually in S or M state.
apr
Does the second diagram mean that main memory is split into two parts and based on which one you are trying to access, you will deal with contention on either 1 bus or 3 buses?
rrp123
I don't see how you wouldn't have to use the interconnect that connect both groups of processors, unless both sets of processors know what the state of the other set of processors is, and what cache lines they have. Otherwise, you'd still have to communicate between both of them to ensure that there would be no stale data stored in the cache of any of the processors.
apr
@rrp123 I agree with you, I think there is information at a higher level that is needed. For example, if there was simply 1 bit per line for the LEFT and RIGHT groups which was a 1 if any of the processors in each group stored that line in S or M state, then only if the bit is 1, would you need to broadcast to those. Otherwise you don't need to broadcast the BusRdX at all. So, potentially, you save time hogging the interconnect by storing some extra information locally.
Why hierarchical snooping helps? Let me try to explain this, please correct me if wrong.
If the right group sends a BusRdX message to the left group, and no processors of left group is in S or M state, then nothing needs to be further broadcast to the left group, potentially saving half broadcast.
However there are cases where the broadcast can't be saved. for example if right group sends BusRdX, and some processor in left group is actually in S or M state.
Does the second diagram mean that main memory is split into two parts and based on which one you are trying to access, you will deal with contention on either 1 bus or 3 buses?
I don't see how you wouldn't have to use the interconnect that connect both groups of processors, unless both sets of processors know what the state of the other set of processors is, and what cache lines they have. Otherwise, you'd still have to communicate between both of them to ensure that there would be no stale data stored in the cache of any of the processors.
@rrp123 I agree with you, I think there is information at a higher level that is needed. For example, if there was simply 1 bit per line for the LEFT and RIGHT groups which was a 1 if any of the processors in each group stored that line in S or M state, then only if the bit is 1, would you need to broadcast to those. Otherwise you don't need to broadcast the BusRdX at all. So, potentially, you save time hogging the interconnect by storing some extra information locally.