When we perform the first access (blue), we load the entire row into the row buffer by performing the precharge (PRE) and row activate (RAS) operations. Since the second access (orange) is on the same row, we do not have to redo PRE and RAS. However, accesses 3 and 4 are on different rows, so we have to do the PRE and RAS operations again.
pk267
The utilization in this case is measured by the proportion of time for which the data pins are busy. This is because data pins are the bottleneck, the critical path in the entire transfer. The utilization here is 40%.
jocelynh
In what situations would this sort of memory access actually occur? Aren't we pretty much always loading full cache lines, which avoids the low pin utilization problem?
jkorn
@jocelynh sure, but even then remember that with optimizations like interleaving addresses across chips, we may only be needing one byte from a single chip at one time. We can do things like burst mode, but the main point is that whenever we aren't loading the same line there is always this decently large period of time that the pins aren't being utilized.
When we perform the first access (blue), we load the entire row into the row buffer by performing the precharge (PRE) and row activate (RAS) operations. Since the second access (orange) is on the same row, we do not have to redo PRE and RAS. However, accesses 3 and 4 are on different rows, so we have to do the PRE and RAS operations again.
The utilization in this case is measured by the proportion of time for which the data pins are busy. This is because data pins are the bottleneck, the critical path in the entire transfer. The utilization here is 40%.
In what situations would this sort of memory access actually occur? Aren't we pretty much always loading full cache lines, which avoids the low pin utilization problem?
@jocelynh sure, but even then remember that with optimizations like interleaving addresses across chips, we may only be needing one byte from a single chip at one time. We can do things like burst mode, but the main point is that whenever we aren't loading the same line there is always this decently large period of time that the pins aren't being utilized.