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Takes 8 cycles to access 64 bits, since only one DRAM is actually sending the data needed


This is a very inefficient usage of the 64 bit bus, since at any point in time, we are only getting 8 bits of information out of the 64 possible bits. If we were trying to fill in a cache line of size 64 bytes, it would take 64 cycles instead of 8 cycles that you would get if we were using all 8 DRAM chips.